Research · Papers · Direct sums, wedges and the p14 frontier · MF-072
Impossibility of rank-tight p5 realizations for q-rank-5 edges
In the rank-tight model G = W, every e ∈ E₅ is p5-impossible
Published 2026-08-29
For everyone
Plain summary
MF-072 tests eight directed cases from an affine-code family, labeled q-rank-5. The test looks for five-product solutions under the rank-tight condition, where the gate functions span only the target space without extra helper dimensions. Each product is an AND gate between two Boolean expressions. All eight cases fail the five-product screen, halting at the stage pattern 1→1→0. The uploaded screen artifact and an independent audit engine agree on all eight cells.
Whether seven-product solutions exist remains open. The register marks two-catalyst existence as UNKNOWN. A six-gate solution would require one catalyst (an added helper dimension), while a minimal seven-gate solution would require two. Curation notes record no corrections and no prior-art position.
Result
Let E₅ be the set of eight q-rank-5 p7-eligible directed affine-code edges in the register. In the rank-tight model G = W, every e ∈ E₅ is p5-impossible.
All eight cells share the flag profile 1→1→0, verified by both the uploaded pack and an independent engine. The register marks p7 two-catalyst existence as UNKNOWN, noting that a six-gate realization requires one catalyst and a minimal seven-gate realization requires two.
Setting and definitions
q-rank-5 designates the eight-edge family. The budget p5 allows five AND gates. W is the target quotient, and G is the quotient space spanned by the gate functions; rank-tight enforces G = W.
The sequence 1→1→0 is the flag profile across all eight rank-tight p5 screens. A catalyst is an independent gate-space direction outside W. The one-catalyst and two-catalyst labels define search spaces for six-gate and seven-gate extensions rather than witnessed constructions.
Method
The eight rank-tight p5 instances were evaluated via flag screens.
This eliminates rank-tight p5 realizations for the entire set. No p7 construction is certified: p7 two-catalyst existence remains UNKNOWN under the one-catalyst (p6) and two-catalyst (minimal p7) extension budgets.
Discussion
MF-072 rules out rank-tight p5 realizations across all eight q-rank-5 p7-eligible edges. The uniform 1→1→0 profile is confirmed by independent audit across every cell, closing the five-product rank-tight search.
The p7 two-catalyst question remains UNKNOWN. The register's budget classifications—one catalyst for six gates, two for a minimal seven-gate circuit—frame future search targets without asserting existence at p6 or p7.
The curation log lists no corrections, restorations, or withdrawals, and records no prior-art position.
For everyone — the takeaway
What this means
None of the eight cases can be built with five AND gates under the rank-tight constraint. Any future search for a seven-product circuit must add extra dimensions to the gate space: one for six gates, or two for a minimal seven-gate design. The entry proves the five-gate limit but leaves open whether six- or seven-gate circuits actually exist. The register lists no prior art for this result.
Register references
- MF-072
- Uploaded
rank5_p5_flag_screens.json - CONT
lens_r2c_independent_audit.json - Prior art: the register does not record this.
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 2 of 2 receipt files bundled (5 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-08-29
- 2026-08-29Published on this site.