Research · Papers · Direct sums, wedges and the p14 frontier · MF-070
Impossibility of p7 realizations for rank-tight q-rank-7 edges under G = W
In the rank-tight model G = W, every e ∈ E₇ is p7-impossible
Published 2026-08-29
For everyone
Plain summary
A comprehensive search tested 32 specific circuit paths, labeled q-rank-7, to see if any could be implemented using seven AND gates without extra helper directions (the rank-tight condition G = W). None succeeded. Every single path failed at the fourth step, displaying the exact same screening pattern (1→3→1→1→0) and dimension sequence (0→1→2→3→dead). An independent solver engine confirmed the results. This rules out this entire group of compact 7-gate designs when no auxiliary space is allowed.
Result
Let E₇ be the 32 q-rank-7 p7-eligible directed affine-code edges recorded in the Lens C screen. In the rank-tight model G = W, every e ∈ E₇ is p7-impossible: no edge admits a p7 realization.
The live replay yielded 0 successes across the family. All 32 instances follow the shared corrected profile 1→3→1→1→0, with flag dimensions 0→1→2→3→dead. After establishing three independent nonlinear directions, no legal fourth product lies in W. Independent engine checks reproduce the recorded 7→0 and 8→0 outcomes.
Setting and definitions
An affine-code edge is a directed member of the finite affine-code edge family tested in the screen. q-rank-7 designates this 32-edge class, and p7 denotes a budget of seven products (AND gates). W is the target quotient space, while G is the quotient space spanned by the gate functions. The rank-tight condition requires G = W.
The profile tracks successive survivors in the flag screen, and the dimension sequence records flag dimensions through each stage until the failure state dead.
Method
All 32 screens were executed via live replay, yielding 0 successes and the uniform profile 1→3→1→1→0. An independent engine verified the run, matching the recorded 7→0 and 8→0 tallies.
The decisive obstruction occurs at the fourth product: after fixing three independent nonlinear directions, no valid fourth product exists within W under G = W.
The verification artifacts, including the verification receipt and the complete replay package, are available in this paper's downloadable evidence pack.
Discussion
MF-070 eliminates the rank-tight G = W path for all 32 q-rank-7, p7-eligible directed edges. The obstruction is localized precisely at the fourth product step within the flag progression.
This impossibility is strictly confined to G = W. It does not restrict seven-product realizations in an expanded gate space or settings with catalytic directions. The register maintains 1→3→1→1→0 as the corrected profile, with no further corrections, restorations, withdrawals, or prior-art comparisons on record.
For everyone — the takeaway
What this means
You can cross off all 32 of these circuit paths if you are looking for a 7-AND implementation that stays strictly within the target space. Every case hits an insurmountable bottleneck at the fourth gate. If you add auxiliary space or catalyst variables, you are outside this result and need a separate search.
Register references
- MF-070
- CONT
lens_r2c_frontier_verification_receipt.json - Package
replay/frontier_exact_full_replay.json(SHA-256b7cb809b…2df962f3) - Prior art: the register does not record this.
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 2 of 2 receipt files bundled (85 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-08-29
- 2026-08-29Published on this site.