Research · Papers · Direct sums, wedges and the p14 frontier · MF-069
A strict flag characterization of rank-tight acyclic full-domain XAGs
dim W = r admits acyclic full-domain XAG with r AND gates iff ∃ 0 = U0 < ... < Ur = W: Ui / U_{i-1} contains class of Li Ri, Li, Ri in A + U_{i-1}
Published 2026-08-29
For everyone
Plain summary
This paper establishes an exact test for building a specific type of logic circuit. The circuit uses one-way logic made of XOR and AND gates, with affine operations (sums of available signals plus constants) surrounding the AND gates. After factoring out the purely affine behavior of the target outputs, a quotient space of rank r remains, representing the necessary non-linear product directions.
The theorem proves that a circuit can achieve the target with exactly r AND gates if and only if those r directions can be assembled step by step in a strict chain of subspaces. At every step, the next direction must come directly from multiplying two affine combinations of already available signals, allowing for internal factor cancellations. An independent implementation reproduced the author's results across uploaded test cells, and a two-AND disjoint control succeeded. The register lists no prior art.
Result
Let a vector Boolean map have target quotient W with dim W = r. It admits an acyclic full-domain XAG with exactly r AND gates if and only if there exists a strict flag
0 = U0 < U1 < ... < Ur = W
such that each one-dimensional quotient space Ui / U_{i-1} contains the class of a product Li Ri with Li, Ri in A + U_{i-1}, where A is the affine class space. This equivalence accounts for mixed right-factor cancellation inside A + U_{i-1} and provides an exact characterization rather than a lower bound.
Setting and definitions
The target quotient W is the r-dimensional vector space of target classes modulo affine functions. The affine class space available prior to introducing nonlinear products is A. A strict flag is a sequence of subspaces 0 = U0 < U1 < ... < Ur = W where dim Ui = i. At step i, factors Li and Ri are chosen from A + U_{i-1}, with their product evaluated modulo U_{i-1}. The circuit model is an acyclic, full-domain XAG where the total AND gate count equals dim W.
Method
The equivalence is proved by exact frontier reachability on the flag condition: at each frontier i, the subspace A + U_{i-1} fixes the reachable set of product classes that can span a one-dimensional extension Ui / U_{i-1}.
Verification receipts:
- The reachability proof and verification records are available in this paper's downloadable evidence pack.
- A compact reachability implementation matches the author's checker across all uploaded cells.
- An independent audit replay confirms these findings alongside a verified two-AND disjoint positive control, with data provided in the evidence pack.
Discussion
The theorem establishes the exact solvability boundary for the rank-tight regime where the AND budget equals dim W. Because Li and Ri range over the full affine-expanded space A + U_{i-1} at each stage, the flag condition captures all mixed right-factor cancellations within that space.
Practically, the reachability condition serves as a pruning criterion: targets lacking a valid flag can be rejected immediately without running gate-level synthesis searches, while valid flags yield explicit topological orderings for quotient direction synthesis. The characterization is specific to acyclic full-domain XAGs operating at the minimal budget r; it does not govern over-budget circuits with more than r AND gates or alternate circuit topologies.
For everyone — the takeaway
What this means
Finding an optimal circuit can be hard, but when the gate budget matches the number of non-linear directions, this theorem turns the search into a step-by-step checklist. You start with the basic affine inputs. If you can multiply two available signals to create a new required output direction, you add that direction to your pool and repeat. If you reach all r directions, an r-gate circuit is guaranteed to exist; if you get stuck at any step, no such circuit can exist at that exact gate count.
Register references
- Entry: MF-069
- Receipt artifacts: CONT
lens_r2c_frontier_verification_report.md;lens_r2c_independent_audit.json;zkgolf-r2-frontier-c-breakthrough/frontier_exact.py - Prior-art works: none recorded in register
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 3 of 3 receipt files bundled (13 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-08-29
- 2026-08-29Published on this site.