Research · Papers · Adders, counters and the heap law · ML-087
Multiplicative complexity of cascaded k:2 carry-save compressor slices
MC(k:2) = k - 2 for cascaded Full Adder compressor slices in the sequential XAG model (MC(4:2)=2, MC(5:2)=3, MC(6:2)=4)
Published 2026-09-04
For everyone
Plain summary
Carry-save compressors combine multiple binary numbers without waiting for carries to ripple across every bit position. A k-to-2 compressor slice takes k input bits and reduces them to two outputs—a sum bit and a carry bit—by chaining k-2 Full Adders in a row. In privacy-preserving computation and cryptographic protocols, non-linear logic gates (AND gates) drive most of the computational cost. The minimum number of AND gates needed to evaluate a function is called its multiplicative complexity.
This paper proves that a cascaded k-to-2 compressor slice requires exactly k-2 AND gates. Even though later adders can read carry signals from earlier adders in the chain, those earlier signals cannot cancel or replace any downstream AND gates. Each added stage requires its own independent non-linear operation, so standard cascades cannot compress k bits using fewer than k-2 multiplications.
Result
For standard k:2 carry-save compressor slices constructed from k-2 cascaded Full Adders evaluated in the sequential XOR-AND Graph (XAG) model:
MC(k:2) = k - 2
Specifically, MC(4:2) = 2, MC(5:2) = 3, and MC(6:2) = 4.
Intermediate Full Adder carry outputs do not act catalytically to lower the multiplicative complexity of downstream stages. Pairwise bilinear cross-terms generated between existing intermediate carry signals and fresh primary inputs have disjoint algebraic support across stages, compelling each successive Full Adder stage to introduce a linearly independent AND gate.
Setting and definitions
Let GF(2) denote the two-element Galois field, with addition over XOR and multiplication over AND.
A standard cascaded k:2 carry-save compressor slice computes a multi-operand reduction of k primary inputs into 2 outputs (a sum bit and a carry bit) via a sequence of k-2 cascaded Full Adder stages.
The metric MC(f) denotes the multiplicative complexity of a multi-output Boolean function f over the standard base (XOR, AND, NOT), defined as the minimum number of 2-input AND gates required in an XAG to evaluate f over GF(2), assuming zero cost for XOR and NOT operations. The cost evaluation operates in the sequential XAG and bilinear/tensor rank model.
Method
Exact gate count bounds and algebraic analyses are recorded in the corridor sweep receipt:
programs/corridor-sweep-20260901/wave2-compressors/compressor_results.json
Each stage i (from 1 to k-2) introduces fresh primary inputs whose degree-2 bilinear cross-terms cannot be formed as linear combinations of outputs from previously evaluated AND gates. Because the algebraic support of these cross-terms is disjoint from intermediate carry outputs of earlier stages, the tensor rank increases strictly by 1 for each added Full Adder stage, ruling out catalytic gate cancellation across the chain.
Discussion
This result applies to cascaded k:2 carry-save compressor slices formed by sequential Full Adder chains under the sequential XAG model.
Carry-chain non-catalysis is structural for sequential cascades: intermediate carry signals cannot reduce the multiplicative complexity below the baseline of one AND gate per Full Adder.
For arithmetic synthesis tools and compressor tree architectures, optimizations targeting AND-depth or multiplicative complexity cannot achieve sub-linear AND counts by reusing internal carry nets within purely cascaded k:2 slice topologies.
For everyone — the takeaway
What this means
Chaining k-2 Full Adders in sequence to compress multiple binary inputs always requires one AND gate per stage. In zero-knowledge proofs and secure multi-party computation, where non-linear operations carry heavy performance penalties, serial cascades offer no way to share or eliminate AND gates. Designers seeking to lower non-linear gate counts must switch to alternative tree topologies rather than expecting carry reuse to save gates in standard cascades.
Register references
- Register entry: ML-087
- Receipt artifact: programs/corridor-sweep-20260901/wave2-compressors/compressor_results.json
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 1 of 1 receipt files bundled (1 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-09-04
- 2026-09-04Published on this site.