Research · Papers · Cipher S-boxes, χ, and quantum gate counts · ML-017
Universal wrong row-0 assignments in Toffoli-lift cyclic p6 modules
All 15 qdim-6 modules in the Toffoli-lift cyclic p6 family attain full rank and admit a universal wrong row-0 assignment
Published 2026-08-29
For everyone
Plain summary
This entry closes a route toward building reversible logic circuits. It tested 15 candidate modules in the Toffoli-lift cyclic p6 family, each at size qdim-6. Every module reached full rank, passing the test for independent entries. However, every module also admitted a bad row-0 assignment that caused the construction to fail. Because all 15 modules shared this failure, this specific route is marked EXHAUSTED. The finding applies only to this family. The register lists no evidence package, solver log, certificate, replay script, or prior-art citation for ML-017.
Result
Within the Toffoli-lift cyclic p6 family, all 15 qdim-6 modules attain full rank, and each admits a universal wrong row-0 assignment. Status: EXHAUSTED.
Setting and definitions
Module size is designated qdim-6. The rank condition denotes full row rank across the module. A row-0 assignment assigns values on index 0; universality denotes admission across all 15 modules; wrong indicates failure to satisfy the target exact relation. The register records no additional parameters.
Method
The register logs the 15-module outcome without documenting an encoding, solver execution, certificate, replay script, formal argument, or receipt artifact. Evidence: none stated.
Discussion
Scope is restricted to the 15-module cyclic p6 family. Because full rank coexists with a universal wrong row-0 assignment across all candidates, the route is EXHAUSTED. The result does not constrain other synthesis routes. Corrections: NONE; the INDEX corrections section contains no ML-017 entry. Prior-art position: none recorded.
For everyone — the takeaway
What this means
This specific circuit design route is a dead end. All 15 modules passed the independence test by hitting full rank, but full rank was not enough to guarantee a working circuit. Each module permitted a flawed row-0 assignment that broke the construction. The cyclic p6 route is exhausted, though other reversible design strategies remain open. The register does not provide an artifact package to retrace these calculations.
Register references
- ML-017
- Receipt artifact: the register does not record this.
- Prior-art work: the register does not record this.
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 0 of 0 receipt files bundled (1 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-08-29
- 2026-08-29Published on this site.