Research · Papers · The quadratic hull and its defects · MF-165
Equality of multiplicative and quadratic complexity for 3-spaces on at most 5 variables
MC(W) = qMC(W) for all 3-dimensional spaces W <= Quad(n) with n <= 5 in the general XAG model.
Published 2026-09-04
For everyone
Plain summary
In Boolean logic circuits, additions (XOR) are cheap, while multiplications (AND) are expensive. A function's multiplicative complexity is the fewest AND gates needed to evaluate it. For quadratic formulas—where at most two inputs multiply together in any term—circuit designers often ask whether computing cubic or quartic intermediate terms can reduce the total number of AND gates needed.
This work proves that for any three-dimensional linear space of quadratic formulas on up to five variables, higher-degree intermediate steps never save multiplications. The general multiplicative complexity always equals the quadratic multiplicative complexity. This resolves a question left open by Boyar and Find for small dimensions. A prior small-variable exhaustive check was not verified against literature due to lack of external network access during auditing.
Result
For every 3-dimensional subspace W <= Quad(n) of quadratic forms on n <= 5 variables over GF(2), the general multiplicative complexity equals the quadratic multiplicative complexity in the general XOR-AND graph (XAG) model:
MC(W) = qMC(W)
Setting and definitions
Let Quad(n) denote the vector space of quadratic Boolean forms over GF(2) on n variables x0, ..., x(n-1). For a subspace W <= Quad(n), the multiplicative complexity MC(W) is the minimum number of AND gates in an XAG computing a basis of W, with intermediate gate outputs unrestricted in algebraic degree. The quadratic multiplicative complexity qMC(W) restricts all gate outputs to Quad(n).
The action of GL(n,2) by linear change of basis preserves both MC and qMC on Quad(n).
Method
Certified exhaustive chained-circuit enumeration modulo GL(n,2) symmetry establishes MC(W) = qMC(W):
- Canonical normalisation: GL(n,2) invariance fixes the first AND gate to x0 x1. Intermediate gates carried arbitrary degree; 5,798 of 10,377 recall-control circuits reaching a 3-dimensional quadratic span contained cubic or quartic gate classes.
- Layer k = 3 enumeration (n = 5): Evaluating 15,623,307 circuits in 96 s identified 6,818 reachable 3-dimensional quadratic spans W, every one satisfying qMC(W) <= 3.
- Layer k = 4 evaluation and state reduction (n = 5): Evaluating 383,114,550 gate-4 candidate extensions across 11,830 canonical 3-gate states yielded 1,298,067 distinct 3-dimensional spans W, all satisfying qMC(W) <= 4. Replay during audit reproduced bit-identical state sets.
- 4-AND state-reduction lemma: For any W <= Quad(S_4) with dim W = 3 and maximal qMC(W), dim(W ∩ Quad(S_3)) >= 2, and every plane P' <= W ∩ Quad(S_3) satisfies qMC(P') >= qMC(W) - max_mc. Certification across 68,743 planted test instances confirmed a 1,320-fold search-space reduction.
- Bound closure: Every plane among the 174,251 quadratic planes at n = 5 satisfies qMC ∈ {2, 3} (9,765 planes have qMC = 2; 164,486 planes have qMC = 3). The maximum quadratic complexity over any 3-dimensional space W at n = 5 is at most 3 + 2 = 5, realized in 580 of 60,000 random draws. Because circuits with MC(W) <= 4 achieve qMC(W) <= 4 by the k <= 4 enumeration, and spaces with MC(W) >= 5 match qMC(W) = 5, counterexamples cannot exist.
The proof does not rely on Mirwald–Schnorr theory.
Discussion
The transfer equality MC(W) = qMC(W) holds unconditionally for dim W = 3 and n <= 5.
Mirwald and Schnorr (1992) proved transfer equality for dim W <= 2. Boyar and Find noted dim W >= 3 as open. Novelty of this check for n <= 5 was not cross-referenced against unindexed literature because the recording seat lacked external network connectivity and skipped prior-art routing.
Alongside MF-166, the data shows that any potential transfer gap between MC and qMC requires planes of W to be light relative to W itself. For instance, all 105 spaces at n = 4 with lower bound LB = 3 < 4 = qMC satisfy MC = qMC = 4.
Scaling this exhaustive instrument to n = 6 fails under the current framework, as documented in ML-075.
For everyone — the takeaway
What this means
Multiplication gates are the primary cost bottleneck in secure multi-party computation, zero-knowledge proofs, and hardware circuit synthesis. For three quadratic equations on up to five inputs, circuit designers do not need to test cubic or higher-degree intermediate formulas to minimize AND gate counts. Searching purely quadratic intermediate steps is guaranteed to find the most efficient circuit.
Attribution and prior art
Prior art: The result for dim W <= 2 is known from Mirwald–Schnorr (1992), while Boyar–Find record dim >= 3 as open. Novelty regarding prior exhaustive checks for small n remains unverified in existing literature.
Register references
- Register entry: MF-165
- Related entries: MF-166, ML-075
- Prior-art citations: Mirwald–Schnorr (1992); Boyar–Find
- Receipt artifacts: wave1-ms3/REPORT.md §2 U1; n4_dim3.json, n5_k3_circuits.json, n5_k4_reachW.pkl, n5_k4_replay.json, audit_u1.json, audit_u1b.json, u1c_negctrl.json, states_n5b.py, run_k4_n5.py, PROGRESS.log lines 62–126 and 04:00–04:10Z block
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Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 10 of 10 receipt files bundled (35 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-09-04
- 2026-09-04Published on this site.