Research · Papers · Adders, counters and the heap law · MF-139
Gate-class dimension increment per C7 column
For c ∈ {2,3,4}, C7 c-column target requires 3 new gate-class dimensions beyond the 3(c-1)-gate prefix, giving exact cost 3c under prefix constraint
Published 2026-09-04
For everyone
Plain summary
When building logic circuits, a key question is how many multiplication operations (AND gates) are needed as the circuit grows. For the C7 circuit family, adding another column adds three functional dimensions that the previous stage cannot produce. Since each AND gate can add at most one dimension, any circuit built by extending the standard prefix must use three more gates per column, fixing the cost at 3c gates for c = 2, 3, and 4. This is a direct mathematical proof, not a brute-force computer search. It applies only to circuits that keep the standard prefix layout, not to designs built from scratch.
Result
For c ∈ {2, 3, 4}, the C7 c-column target requires exactly 3 new gate-class dimensions beyond the linear span of the natural 3(c-1)-gate prefix. In the GF(2) XAG model, one AND gate supplies at most one dimension; therefore, any circuit embedding the natural 3(c-1)-gate prefix has exact multiplicative complexity 3c.
Setting and definitions
Complexity is measured in the GF(2) XAG model, where XOR gates are free and cost equals the number of AND gates.
The target is the c-column specification of the verified C7 circuit family. The natural prefix is the canonical 3(c-1)-gate realization of the (c-1)-column subtarget. Gate-class dimension is the GF(2) linear dimension of the subspace spanned by gate outputs. Each AND gate increases this reachable dimension by at most 1.
Method
The dimension increment is computed algebraically without SAT solvers for c = 2, 3, and 4 by projecting the c-column target outputs onto the GF(2) span of the 3(c-1)-gate prefix.
Controls verify that the (c-1)-column target has rank deficiency 0 against its own 3(c-1)-gate prefix. Testing the c-column target against the (c-1)-column prefix span yields a rank deficiency of exactly 3 across all tested widths.
Evidence tier: FC with controls. Executed via:
zkgolf-decomp/record-scratch/wider_seam/prefix2.pyc7_correct.pygate_rank.pyzkgolf-decomp/RECORD-WIDER-SEAM-PROGRESS.log
Discussion
This closes the multiplicative complexity of C7 implementations constrained to contain the natural prefix chain at exactly 3c gates. It does not restrict non-prefix architectures.
At c = 2, dimension counting independently recovers the 6-gate bound of MF-138 analytically, bypassing both SAT search and the packing lemma.
For everyone — the takeaway
What this means
This sets a hard floor on modular C7 designs. If you build a larger circuit by appending logic to the standard smaller block, every new column demands exactly three more AND gates. No algebraic trick can shrink that cost while keeping the prefix intact. Beating 3c gates requires throwing out the standard prefix and redesigning the circuit from scratch.
Register references
- Register entry: MF-139
- Cross-referenced entry: MF-138
- Receipt script:
zkgolf-decomp/record-scratch/wider_seam/prefix2.py - Receipt script:
c7_correct.py - Receipt script:
gate_rank.py - Log receipt:
zkgolf-decomp/RECORD-WIDER-SEAM-PROGRESS.log
Every artifact named above is bundled in, or hashed by, this paper's evidence pack below.
Evidence pack
Everything needed to check this entry against its receipts: the register text, a manifest with a SHA-256 hash for every named receipt, and 0 of 4 receipt files bundled (1 KB). Anything not bundled is still hashed in the manifest and lives in the compute-box working trees.
Changelog
Last reviewed 2026-09-04
- 2026-09-04Published on this site.